Use MMU, Memory Management Unit to translate the address.

Overview

MMU itself will not store page table, it will lookup page table in memory, it will use TLB as a cache.

TLB

translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location.1 It can be called an address-translation cache. It is a part of the chip’s memory-management unit (MMU).
A TLB may reside between the CPU and the CPU cache, between CPU cache and the main memory or between the different levels of the multi-level cache. The majority of desktop, laptop, and server processors include one or more TLBs in the memory-management hardware, and it is nearly always present in any processor that utilizes paged or segmented virtual memory.